We use all the standard Verilog and VHDL simulation tools from Cadence, Synopsys, and Siemens EDA. We are expert at high-speed digital designs including memories and processor designs using custom or standard digital interconnects such as Enet, PCIe, USB 3+, and others.

With today’s complex digital ASICs and FPGAs, functional verification is essential. We work to ensure 100% functional coverage to all our designs. We use the latest methodologies such CRV and functional checkers. Further we can use your tools or verify your design using our own tools.

We have highly experienced and knowledgeable analog designers, skilled in the standard schematic capture tools and SPICE simulation tools from vendors such as Cadence and Synopsys.

Functional verification across the digital to analog domain is complex and very dependent on the analog modeling of the analog circuits. We provide these services using Verilog-A or modeling with C++. We then can write the directed tests and the randomized tests to have extremely high confidence in the design functioning to specification.

We provide porting services to port your analog or digital libraries (PDKs) to a new technology node or to a new foundry vendor’s node. Ask us for a proposal.

We can provide staff level analog design support or a team to develop a block or the entire analog portion of the design.

We are adept at the latest design nodes using FinFET technologies. Our layout teams have been working in FinFET for over 10 years. We can help you develop reliable design rules with your design team to prevent DRC and ERC violations downstream in the release cycle.

We also have extensive design and layout experience at high voltage (HV) technologies. We have worked with up to 100v designs using processes from Tower Semiconductor (formerly TowerJazz), Global Foundries (GF), Analog Devices (ADI), TSMC, and others.

We can provide Design For Test (DFT) capabilities to automatically connect the Scan chains and rout them to the JTAG or SLT (System Level Test) IO pins.

We understand the backend tools and the PDKs for the foundries where your ASIC will be fabricated. We adapt the foundries best practices for DFM such that you will get the yields you expect.

Early in the design cycle we work with the design team to floorplan the ASIC. As the design progresses the floorplan is continually updated. We can do the Physical Design (PD) digital Place and Route (PnR) of your digital block or stitch together the blocks and IO at the chip level. This PnR is first done before the design is completed to identify routing bottlenecks which may result in modification to the floorplan. All while holding to the performance requirements and DRC and ERC success. Timing convergence at the top level is the most critical step in the release process. We’ll work with you to have performance budgets at each level of the ASIC hierarchy such that at the top level the chip will meet specifications.

Most semiconductors today have a micro-engine embedded. This could be an off the shelf design soft design (client does the PD) or a hardened processor block such as ARM or RISC V (the PD at the required process node is completed and validated). We’ll make sure that the earlier floor planning has optimized the placement of the processor for maximum performance.