Siliance

ASIC/FPGA Design Verification Jobs

Below is a listing of jobs currently available in design verification of ASIC's and FPGA's at the block and system level with siliance.  Please submit your resume if you qualify.

Principal FPGA Design Verification Engineer

Job Description

siliance has several design verification (DV) projects up that will require expert verification of complex FPGAs and muliple FPGA based systems. You will use primarily SystemVerilog (SV) verification language (and possibly some C++ or SystemC ) to verify our customer's designs. You will work as a full time employee of Siliance or as a 1099 contractor when appropriate. Tasks include:

  • Migrate/redesign the existing DV environment to SV
  • Write the verification test plan
  • Specify and develop the verification environment and transactors using SystemVerilog.
  • May convert tests in Vera, Specman e, or other languages to SystemVerilog.
  • May develop high level un-timed transaction models in C++ or SystemC.
  • May develop bus functional models in Verilog or VHDL
  • Develop regressable, self-checking test suites to implement the test plan.
  • Functional verification using SVA required.
  • Isolate design failures and assist in bug resolution.

Requirements

  • 10 years overall experience in logical design verification
  • Have successfully defined, developed, and used multiple verification environments
  • Functional verification experience required.
  • Experienced team leader, able to set technical direction and guide onshore or offshore team members
  • Experience with SystemVerilog is required.  OVM and UVM experience a plus.
  • Experience with coverage monitors and constraint based randomization
  • Experience with SVA assertions is required

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Principal ASIC Design Verification Engineer

Job Description

Looking for a seasoned professional verifiers or designer/verifiers, who has experience with SystemVerilog verification techniques. This position plays a key role in verifying a highly complex processor design with good skills in communicating results and ensuring timely completion of the program.

Requirements

  • Have 8+ years experience in DV.
  • Must have SystemVerilog experience.  OVM and/or UVM is a plus.
  • IEEE Floating Point standard experience would be a plus.
  • Processor verification of any type experience is strongly preferred.
  • Verification where the embedded code is as-much-as or the-greater source of stimulus for the design than external BFMs, is relevant experience for us
  • Experience with custom or commercial FPGA emulation board, to functionally duplicate what will eventually be in the ASIC.

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Senior FPGA Verification Engineer

Job Description

siliance has projects that require design verification of complex FPGAs and muliple FPGA systems. You will use SystemVerilog  to verify our customer's designs. You will work as an employee of siliance.

Tasks include:

  • Determine verification methodology and environment
  • Participate in writing the verification test plan
  • Develop tests in SystemVerilog (OVM or UVM a plus)
  • May develop high level functional transaction models in C++ and SystemC.
  • May develop bus functional models in Verilog or VHDL
  • Develop regressable, self-checking test suites to implement the test plan.
  • Isolate design failures and assist in bug resolution.

Requirements:

  • 4+ years overall experience in logical verification
  • Have successfully used SystemVerilog DV environments
  • Experience with coverage monitors and constraint based randomization
  • Experience with SVA assertions
  • Experience with media processing and consumer electronics is a plus.

Submit Your Resume

Senior FPGA Design Verification Engineer

Job Description

Siliance has DV projects that will require verification of complex FPGAs. You will use primarily SystemVerilog (SV) OVM to verify our customer's designs. You will work as a full time employee of Siliance, either individually or as part of a Siliance team.

Tasks include:

  • Evolve  the existing SV DV environment to support new functions
  • Assist the writing of the verification test plan
  • May develop bus functional models and new transactors. 
  • Develop regressable, self-checking test suites to implement the test plan.
  • Implement functional verification plan (using SVA) to achieve very high functional coverage.
  • Isolate design failures and assist in bug resolution.

Requirements

  • 5+ years overall experience in design verification
  • Functional verification techniques required.
  • Experience with SystemVerilog is required.  OVM and/or UVM experience a plus.
  • Experience with coverage monitors and constraint based randomization 
  • Experience with SVA assertions is required

Submit Your Resume

Senior ASIC Design Verification Engineer

Job Description

siliance has DV projects that will require verification of complex ASICs, FPGAs, and systems. You will use C++, SystemC or SystemVerilog to verify our customer's designs. You will work as a full time employee of siliance

Tasks include:

  • Evolve or redesign existing DV environment
  • Assist the writing of the verification test plan
  • Specify, develop, or enhance the verification environment and transactors using SV.
  • May develop bus functional models 
  • Develop regressable, self-checking test suites to implement the test plan.
  • Isolate design failures and assist in bug resolution.

Requirements

  • 5+ years overall experience in design verification
  • Functional verification techniques required.
  • Experience with SystemVerilog is required.  OVM and UVM experience a plus.
  • Experience with coverage monitors and constraint based randomization 
  • Experience with SVA assertions is required

Submit Your Resume

 

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