Siliance

ASIC/FPGA Design Jobs

Below is a listing of jobs currently available in digital ASIC, SoC and FPGA design with siliance.  Please submit your resume if you qualify. 

Senior ASIC/FPGA Design Engineer

Job Description

Individual contributor working on a team of other Logic/RTL engineers responsible for delivering functional programmable logic devices into the lab and integrating these with other hardware functions as well as with the embedded SW team.

  • Documentation and specification generation.
  • Reviewing of test plans, and final approval of product for release.
  • Working with and within the hardware team, collaborating with the DV team to ensure the intent of the design is delivered on time and bug free.

Requirements

  • 6+ years experience with RTL development (Verilog or VHDL) targeting either ASICS or FPGA (Xilinx or Altera) devices.
  • 6+ years of Verilog coding experience. Knowledge of Xilinx and/or Altera FPGA tools, chips and architectures.
  • 6+ years experience coding state machines, DMA engines, packet switching elements and/or high speed (250Mhz internal, 2.5Ghz I/O) logic circuits.
  • 4+ years working in a lab environment.

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Senior ASIC/FPGA Design Engineer

Job Description

You will develop RTL code to implement FPGA-based digital designs, working from specification through to system integration. Projects will range from small through multi-million gates. Most projects implement a combination of control logic (bus interfaces and state machines), Digital Signal Processing, and Embedded Processors. You will work as a full time employee of siliance, either individually or as part of a siliance team, consulting to siliance's clients.

Responsibilities include:

  • Write functional specifications
  • Functional partitioning, block diagram, and detailed design spec
  • RTL coding of design in Verilog or VHDL
  • Develop testbench and verify at the block level
  • Synthesis, mapping to target device, and timing closure
  • May include modeling with Matlab or C++
  • May include lab debug or HW/SW integration

Requirements:

  • 5+ years experience, including successful completion of multiple FPGA implementations
  • Experience targeting Xilinx and/or Altera FPGAs is required.
  • Familiarity with Synopsys, Xilinx ISE, and Altera Quartus tools
  • Coding experience in Verilog and VHDL is required.
  • Implementation of designs with multiple clock domains is required
  • Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
  • Experience implementing DSP algorithms in RTL is preferred
  • Experience interfacing with ARM, ARC, MIPS or PowerPC is preferred

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Senior FPGA Physical Design Engineer

Job Description

Working as part of a team you will develop some RTL code to implement FPGA-based digital designs, working from specification.  Most of your effort will be the place and routing of the FPGA and ensuring that the design will meet all the timing and performance requirements including power performance.  Projects will generally be FPGA’s using multi-million gates. Most projects implement a combination of control logic (bus interfaces and state machines), Digital Signal Processing, and Embedded Processors. You will work as a full time employee of Siliance or as a 1099 contractor consulting to Siliance’s clients.

Responsibilities include:

  • Write functional specifications as required
  • Write detailed design specs asrequired
  • RTL coding of design in SystemVerilog, Verilog or VHDL
  • Floorplanning
  • Synthesis, mapping to target device, and timing closure
  • May include modeling with MatLab or C++
  • May include lab debug or HW/SW integration

Requirements

  • 4+ years experience, including successful completion of multiple FPGA implementations
  • Experience targeting Xilinx or Altera FPGAs is required.
  • Familiarity with Synplicity, Xilinx ISE, and Altera Quartus tools
  • Extensive coding experience in Verilog or VHDL is required.
  • Implementation of designs with multiple clock domains is required
  • Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
  • Experience interfacing with ARM, NIOS, MicroBlaze or PowerPC is a plus
  • Lab debug experience a plus.
  • BSEE or BSCS required.  Advanced degree a plus.

Submit Your Resume'

 

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